An integrated circuit (LSI) has a power terminal, a ground terminal, an I/O signal terminal, and an internal circuit on a chip. The integrated circuit chip is housed in a package, and the package is connected to a circuit board. The power terminal, the ground terminal, and the signal terminal of the integrated circuit chip are connected to the corresponding terminals of the package, and additionally connected to the corresponding terminals of the circuit board. Accordingly, if there is a bad connection in the connection between the chip and the package or in the connection between the package and the circuit board, the power terminal and the ground terminal in the integrated circuit chip become an open state.
Even if the power terminal or the ground terminal in the chip is in an open state, it is subject to some type of voltage state via the internal circuit. Nevertheless, since such voltage state is not an appropriate state as a power supply or ground, the internal circuit is no longer able to operate properly. Accordingly, it is necessary to appropriately detect the open state of the power terminal and the ground terminal.
A circuit which detects an open state of a power terminal is described, for example, in Japanese Patent Application Laid-open No. 2000-193709. In addition, Japanese Patent Application Laid-open No. 2009-81307 and Japanese Patent Application Laid-open No. 2003-31672 describe an I/O circuit connected to an I/O terminal.
Since the power terminal or ground terminal of the chip is subject to some kind of voltage state via the internal circuit even if it is in an open state, the open state can be detected by detecting the voltage state thereof. However, if the detection margin is small, there are cases where the open state is erroneously detected when the voltage of the input terminal exceeds the potential of the power terminal or falls below the potential of the ground terminal in a normal connection status.